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Processing Instruction
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#	Item
181	Microsoft Word - SSD1921-application_note-register_table-1.0.doc Add to Reading List Source URL: www.solomon-systech.com Language: English - Date: 2013-02-25 01:23:13 Central processing unit Control register Microcontrollers TI MSP430 Computer architecture Computing Instruction set architectures
182	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: www.accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware
183	This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and shar Add to Reading List Source URL: www.genetic-programming.org Language: English - Date: 2013-06-23 23:45:30 Estimation theory Mathematics Signal processing Econometrics Functional analysis Hölder condition Estimator Continuous function Regression analysis Statistics Mathematical analysis Statistical inference
184	Parallel Architectures and Compilation Techniques PACT 2001 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2001-10-11 10:17:25 Central processing unit Parallel computing Branch predication Instruction set Branch misprediction Superscalar Computer architecture Computing Computer engineering
185	On the Efficiency of Reductions in -SIMD Media Extensions Jesus Corbal, Roger Espasa and Mateo Valero Departament d’Arquitectura de Computadors, Universitat Polit`ecnica de Catalunya–Barcelona, Spain Abstract Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:47:56 Parallel computing X86 instructions Instruction set architectures Digital signal processing SIMD MMX MDMX SSE2 Instruction set Computer architecture Computing Central processing unit
186	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Memo NoApril 1993 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:37 Computer architecture Compiler optimizations Microprocessors Very long instruction word Central processing unit Scheduling Software pipelining Stream processing Multi-core processor Computing Concurrent computing Parallel computing
187	Vector Processors CS252 Graduate Computer Architecture Lecture 20 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:46 Parallel computing Central processing unit Instruction set architectures Supercomputers Acronyms SIMD AltiVec Vector processor Cray-1 Computing Computer architecture Concurrent computing
188	5 Steps of MIPS Datapath Instruction Fetch Next PC Next SEQ PC Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:47 Cache Computing Computer architecture Virtual memory Classic RISC pipeline CPU cache Translation lookaside buffer Motorola 68000 family Computer hardware Central processing unit Computer memory
189	Fine grain Cross-VM Attacks on Xen and VMware are possible! Gorka Irazoqui Apecechea, Mehmet Sinan Inci, Thomas Eisenbarth, Berk Sunar ∗ Worcester Polytechnic Institute {girazoki,msinci,teisenbarth,sunar}@wpi.edu Abst Add to Reading List Source URL: eprint.iacr.org Language: English - Date: 2014-04-07 18:32:56 Advanced Encryption Standard Central processing unit Computer memory Virtual machines CPU cache Hyper-V Timing attack AES instruction set Xen System software Software Computing
190	PCF8563 Real-time clock/calendar Rev. 7 — 23 July 2010 Product data sheet Add to Reading List Source URL: www.embedded-it.de Language: English - Date: 2010-09-23 11:01:37 Central processing unit Microcontroller INT I²C ARM architecture Computer architecture Interrupts Instruction set architectures

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